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HT24LC04 CMOS 4K 2-Wire Serial EEPROM
Features
* Operating voltage: * Partial page write allowed * 16-byte page write modes * Write operation with built-in timer * Hardware controlled write protection * 40-year data retention * 106 erase/write cycles per word * Industrial temperature range (-40C to +85C) * 8-pin DIP/SOP/TSSOP package
2.2V~5.5V for temperature -40C to +85C
* Low power consumption - Operation: 5mA max. - Standby: 2mA max. * Internal organization: 5128 * 2-wire serial interface * Write cycle time: 5ms max. * Automatic erase-before-write operation
General Description
The HT24LC04 is a 4K-bit serial read/write non-volatile memory device using the CMOS floating gate process. Its 4096 bits of memory are organized into 512 words and each word is 8 bits. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. Up to four HT24LC04 devices may be connected to the same two-wire bus. The HT24LC04 is guaranteed for 1M erase/write cycles and 40-year data retention.
Block Diagram
I/O C o n tro l L o g ic X M e m o ry C o n tro l L o g ic E C Page Buf YDEC A0~A2 VCC VSS A d d re s s C o u n te r S ense A M P R /W C o n tro l D
Pin Assignment
A0 A1 A2
EEPROM A rra y
SCL SDA
HV Pum p
1 2 3 4 5 6 7
8
VCC WP SCL SDA
VSS
WP
HT24LC04 8 D IP -A /S O P -A /T S S O P -A
Rev. 1.60
1
May 6, 2010
HT24LC04
Pin Description
Pin Name A0~A2 VSS SDA SCL WP VCC I/O I 3/4 I/O I I 3/4 Address inputs Negative power supply Serial data inputs/output Serial clock data input Write protect Positive power supply Description
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage.............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...............................0C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VCC ICC1 ICC2 VIL VIH VOL ILI ILO ISTB CIN COUT Parameter Operating Voltage Operating Current Operating Current Input Low Voltage Input High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Standby Current Input Capacitance (See Note) Output Capacitance (See Note) Test Conditions VCC 3/4 5V 5V 3/4 3/4 2.4V 5V 5V Conditions -40C to +85C Read at 100kHz Write at 100kHz 3/4 3/4 IOL=2.1mA VIN=0 or VCC VOUT=0 or VCC Min. 2.2 3/4 3/4 -1 0.7VCC 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 5.5 2 5 0.3VCC VCC+0.5 0.4 1 1 2 6 8 Unit V mA mA V V V mA mA mA pF pF
2.2V~ V =0 or V IN CC 5.5V 3/4 3/4 f=1MHz 25C f=1MHz 25C
Note: These parameters are periodically sampled but not 100% tested
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HT24LC04
A.C. Characteristics
Symbol Parameter Remark Standard Mode* Min. fSK tHIGH tLOW tr tf tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tAA tBUF Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time START Condition Setup Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Output Valid from Clock Bus Free Time Input Filter Time Constant (SDA and SCL Pins) Write Cycle Time Note Note After this period the first clock pulse is generated Only relevant for repeated START condition 3/4 3/4 3/4 3/4 Time in which the bus must be free before a new transmission can start Noise suppression time 3/4 3/4 3/4 3/4 3/4 4000 4700 3/4 3/4 4000 4000 0 200 4000 3/4 4700 Max. 100 3/4 3/4 1000 300 3/4 3/4 3/4 3/4 3/4 3500 3/4 VCC=3V10% Min. 3/4 600 1200 3/4 3/4 600 600 0 100 600 3/4 1200 Max. 400 3/4 3/4 300 300 3/4 3/4 3/4 3/4 3/4 900 3/4 VCC=5V10% Unit Min. 3/4 400 600 3/4 3/4 250 250 3/4 100 250 Max. 1000 3/4 3/4 300 100 3/4 3/4 3/4 3/4 3/4 550 3/4 kHz ns ns ns ns ns ns ns ns ns ns ns
50
500
tSP tWR
3/4 3/4
100 5
3/4 3/4
50 5
3/4 3/4
50 5
ns ms
Note:
These parameters are periodically sampled but not 100% tested * The standard mode means VCC= 2.2V to 5.5V at Ta= -40C to +85C For relative timing, refer to timing diagrams
Functional Description
* Serial clock (SCL)
The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device.
* Serial data (SDA)
VSS. When the write protect pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following table. WP Pin Status At VCC At VSS Protect Array Full Array (4K) Normal Read/Write Operations
The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices.
* A0, A1, A2
Memory Organization
* HT24LC04, 4K Serial EEPROM
The HT24LC04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is not connected. (The device addressing is discussed in detail under the Device Addressing section).
* Write protect (WP)
Internally organized with 512 8-bit words, random word addressing requires a 9-bit data word address. Device Operations
* Clock and data transition
The HT24LC04 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when connected to the
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition.
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HT24LC04
* Start condition
A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition Timing diagram).
* Stop condition
The 8th bit of device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state.
1 0 1 0 A2 A1 A0 R /W
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
* Acknowledge
D e v ic e A d d r e s s
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
D a ta a llo w e d to c h a n g e SDA
Write Operations
* Byte write
SCL S ta rt c o n d itio n A d d re s s o r a c k n o w le d g e v a lid NoACK s ta te
S to p c o n d itio n
A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the non-volatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write is completed (refer to Byte write timing).
* Page write
Device Addressing The 4K EEPROM devices require an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to diagram showing the Device Address). This is common to all the EEPROM device. The next three bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These three bits must compare to their corresponding hard-wired input pins. The 4K EEPROM only use the A2 and A1 device address bits with the third bit as a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is not connected.
The 4K device is capable of 16-byte page writes. A page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a ze r o a f t e r e a ch d a t a w o r d r e ce i ve d . T h e microcontroller must terminate the page write sequence with a stop condition. The data word address lower four bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location (refer to Page write timing).
D e v ic e a d d r e s s SDA S S ta rt A2 A1 A0 R /W ACK
W o rd a d d re s s
DATA P ACK ACK S to p
Byte Write Timing
D e v ic e a d d r e s s SDA S P ACK ACK ACK ACK S to p S ta rt W o rd a d d re s s DATA n DATA n+1 DATA n+x
Page Write Timing Rev. 1.60 4 May 6, 2010
HT24LC04
* Acknowledge polling * Current address read
To maximize bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received.
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n to In itia te W r ite C y c le S e n d S ta rt S e n d C o tr o ll B y te w ith R /W = 0
The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll over during read from the last byte of the last memory page to the first byte of the first page. The address roll over during write from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller should respond with a no ACK signal (high) followed by a stop condition (refer to Current read timing).
* Random read
(A C K = 0 )? Yes N e x t O p e r a tio n
No
Acknowledge Polling Flow
* Write protect
A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller should respond with a no ACK signal (high) followed by a stop condition (refer to Random read timing).
The HT24LC04 has a write-protect function and programming will then be inhibited when the WP pin is connected to VCC. Under this mode, the HT24LC04 is used as a serial ROM.
* Read operations
The HT24LC04 supports three read operations, namely, current address read, random address read and sequential read. During read operation execution, the read/write select bit should be set to 1.
D e v ic e a d d r e s s SDA S S ta rt A2 A1 A0 ACK
DATA
S to p P NoACK
Current Read Timing
D e v ic e a d d r e s s SDA S S ta rt
A2 A1 A0
W o rd a d d re s s S ACK
D e v ic e a d d r e s s
DATA
S to p P NoACK
ACK S ta rt
ACK
Random Read Timing
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HT24LC04
* Sequential read
Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data
D e v ic e a d d r e s s SDA S DATA n
words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller responds with a no ACK signal (high) followed by a stop condition.
DATA n+1
DATA n+x
S to p P NoACK
S ta rt
ACK
ACK
Sequential Read Timing
Timing Diagrams
tF SCL tS SDA SDA OUT
U :S T A
tR tL tH
OW D :S T A
tH
IG H
tH
D :D A T
tS
U :D A T
tS tB
U :S T O
tS
P
tA
A
UF
V a lid
V a lid
SCL SDA 8 th b it W o rd n S to p C o n d itio n ACK tW
R
S ta rt C o n d itio n
Note:
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.
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HT24LC04
Package Information
8-pin DIP (300mil) Outline Dimensions
A B
1 4 8 5
H C D E F G I
Symbol A B C D E F G H I Symbol A B C D E F G H I
Dimensions in inch Min. 0.355 0.240 0.125 0.125 0.016 0.050 3/4 0.295 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 0.375 Dimensions in mm Min. 9.02 6.10 3.18 3.18 0.41 1.27 3/4 7.49 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 9.53 Max. 9.53 6.60 3.43 3.68 0.51 1.78 3/4 8.00 3/4 Max. 0.375 0.260 0.135 0.145 0.020 0.070 3/4 0.315 3/4
Rev. 1.60
7
May 6, 2010
HT24LC04
8-pin SOP (150mil) Outline Dimensions
A 1
8
5 B 4
C
C' G D E F
H
=
* MS-012
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.228 0.150 0.012 0.188 3/4 3/4 0.004 0.016 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.050 3/4 3/4 3/4 3/4 Dimensions in mm Min. 5.79 3.81 0.30 4.78 3/4 3/4 0.10 0.41 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 1.27 3/4 3/4 3/4 3/4 Max. 6.20 3.99 0.51 5.00 1.75 3/4 0.25 1.27 0.25 8 Max. 0.244 0.157 0.020 0.197 0.069 3/4 0.010 0.050 0.010 8
Rev. 1.60
8
May 6, 2010
HT24LC04
8-pin TSSOP Outline Dimensions
8
5 E1
1
4
D A e R 0 .1 0 B y (4 C O R N E R S ) A1 A2 C L
E
L1
G
Symbol A A1 A2 B C D E E1 e L L1 y q Symbol A A1 A2 B C D E E1 e L L1 y q
Dimensions in inch Min. 0.041 0.002 0.031 3/4 0.004 0.114 0.244 0.169 3/4 0.020 0.035 3/4 0 Nom. 3/4 3/4 3/4 0.010 3/4 3/4 3/4 3/4 0.026 3/4 3/4 3/4 3/4 Dimensions in mm Min. 1.05 0.05 0.80 3/4 0.11 2.90 6.20 4.30 3/4 0.50 0.90 3/4 0 Nom. 3/4 3/4 3/4 0.25 3/4 3/4 3/4 3/4 0.65 3/4 3/4 3/4 3/4 Max. 1.20 0.15 1.05 3/4 0.15 3.10 6.60 4.50 3/4 0.70 1.10 0.10 8 Max. 0.047 0.006 0.041 3/4 0.006 0.122 0.260 0.177 3/4 0.028 0.043 0.004 8
Rev. 1.60
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May 6, 2010
HT24LC04
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 8N, TSSOP 8L Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0+0.5/-0.2 2.00.5 12.8+0.3/-0.2 18.20.2
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HT24LC04
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P A0
K0
R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .
SOP 8N Symbol W P E F D D1 P0 P1 A0 B0 K0 t C TSSOP 8L Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 12.0+0.3/-0.1 8.00.1 1.750.10 5.50.5 1.5+0.1/-0.0 1.5+0.1/-0.0 4.00.1 2.00.1 7.00.1 3.60.1 1.60.1 0.3000.013 9.30.1 Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 12.0+0.3/-0.1 8.00.1 1.750.1 5.50.1 1.550.10 1.50+0.25 4.00.1 2.00.1 6.40.1 5.20.1 2.10.1 0.300.05 9.30.1
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HT24LC04
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.60
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May 6, 2010

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